LIBRARY IEEE;
USE IEEE.std_logic_1164.all;

ENTITY microram IS
	PORT (  CLOCK   : IN STD_LOGIC ;
		ADDRESS	: IN STD_LOGIC_VECTOR (8 DOWNTO 0);
		DATAOUT : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
		DATAIN  : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
		WE	: IN STD_LOGIC 
	);
END ENTITY microram;

ARCHITECTURE a OF microram IS
	-------------- Declare the 512x8 RAM component
	component cpuram
		port (
		clka: IN std_logic;
		dina: IN std_logic_VECTOR(15 downto 0);
		addra: IN std_logic_VECTOR(8 downto 0);
		wea: IN std_logic_VECTOR(0 downto 0);
		douta: OUT std_logic_VECTOR(15 downto 0));
	end component;
BEGIN
	------------------- Instantiate the RAM component
	U1 : cpuram
	PORT MAP (clka => CLOCK, dina => DATAIN, addra => ADDRESS,
	         wea(0) => we, douta => DATAOUT);
END ARCHITECTURE a;

